Portable computing devices (e.g., cellular telephones, smartphones, tablet computers, portable digital assistants (PDAs), portable game consoles, wearable devices, and other battery-powered devices) and other computing devices continue to offer an ever-expanding array of features and services, and provide users with unprecedented levels of access to information, resources, and communications. To keep pace with these service enhancements, such devices have become more powerful and more complex. Portable computing devices now commonly include a system on chip (SoC) comprising one or more chip components embedded on a single substrate (e.g., one or more central processing units (CPUs), a graphics processing unit (GPU), digital signal processors, etc.). The SoC may be coupled to one or more volatile memory modules or devices, such as, dynamic random access memory (DRAM) via double data rate (DDR) high-performance data and control interface(s).
Memory, memory bus, and system interconnect power may be a significant source of system power consumption. As known in the art, memory, memory bus, and system interconnect power is a function of the frequency of operation. Higher frequency produces more power consumption. The frequencies of the memory, memory bus and on-chip interconnect are a function of the bandwidth required by each memory client in the system.
In current SoC systems, the operating frequencies of the memory, memory bus, and system interconnect are typically set according to use cases based on a required bandwidth for each use case. The required bandwidth determines the frequencies and the SoC voltage corner used for the SOC, the volatile memory, and associated bus. Frequency and/or voltage settings for providing the required bandwidth translate to a memory and SOC power cost. In existing systems, hardware and/or software is used to dynamically change required frequencies and voltages based on use case.
Two methods are typically used to set a memory bandwidth vote according to use cases. Each method, however, suffers from the tradeoff limitation between conserving memory and SOC power or maintaining desirable performance. In a first method, a memory bandwidth vote is based on a known worst-case (highest) required bandwidth, which may not reap the benefit of frequency and/or voltage savings. In a second method, the memory bandwidth vote is based on an estimated typical (or average) bandwidth. If the estimated bandwidth is too optimistic, the actual bandwidth may exceed system bandwidth, resulting in degradation in performance. If the estimated bandwidth is too pessimistic, the system may not reap the benefit of voltage savings.
Accordingly, there is a need for systems and methods for controlling memory, memory bus, and/or system interconnect frequency with improved power and performance.